(1) FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits, more particularly to field effect transistors and measurements performed thereon.
(2) DESCRIPTION OF THE PRIOR ART
Field Effect Transistors (FETs), in their simplest form, comprise a body of semiconducting material, usually silicon, having two regions of opposite conductivity type to its own, embedded within it and spaced a short distance apart. Said regions of opposite conductivity type are referred to as source and drain regions, the region between them being referred to as the gate region. In most FET designs the gate region further comprises a thin layer of insulating material on the semiconductor surface (usually its oxide) covered with a layer of a contact material (often polycrystalline silicon). Electrically separate electrodes contact all three regions.
Normally, when voltage is applied between source and drain, very little current flows since one of the two PN junctions (relative to the silicon body) will always be back biassed. When, however, the positive voltage becomes large enough it will generate a gate tunneling current. This tunneling current will flow into the depletion region where it acts as an impact ionization source to drive its parasitic bipolar on and go into snap lock (a sharp drop in voltage).
In FIG. 1 we show a schematic cross-section of a type of FET known as an LDD (lightly doped drain). Silicon substrate 1 is P type so that source and drain regions 2 and 3 are N type. Gate insulation layer 4 is contacted through gate electrode 8. Oxide spacers 5 are disposed on either side of gate electrode 10.
Extending from the edges of regions 2 and 3, and lying directly below the spacers, are shallow, lightly doped N regions 6 that define the width of the gate channel. Regions 6 are there for the purpose of improving the performance characteristics of the FET. In a commonly used configuration, source 2 is contacted through grounded electrode 7. The incoming signal that is to be amplified is applied to electrode 8 and the amplified signal read at drain electrode 9.
Most of the FETs of the type just described are mass produced as components within integrated circuits. As a normal part of manufacturing it is necessary, from time to time, to perform measurements on individual FETs, including some of their internal parts. This could be for the purpose of quality control, process control, or trouble shooting, to name a few possibilities. One such measurement is the thickness of the gate insulation layer (4 in FIG. 1).
Thin insulating layers of the type that form gate insulation layers in an FET are most commonly measured by one of several types of non-destructive optical methods, such as ellipsometry or interferometry. These methods all require that at least one surface of the layer being measured be uncovered so they are only applicable prior to the formation of the gate electrode (10 in FIG. 1). This is a severe limitation when used as part of a manufacturing process.
Another possible method for determining gate insulation layer thickness is through a capacitance measurement. This method does not involve removal of the gate electrode but does require a precise value for the area of the gate electrode (assuming, reasonably, that the dielectric constant of the insulating layer is known). In practice, determination of the area to any degree of precision, would be either very time consuming or impossible.